1. Field of the Invention
The present invention relates to a data retention circuit such as a flip-flop circuit, a latch circuit, or the like. More particularly, it relates to a semiconductor memory device provided with static memory cells each using a flip-flop circuit, i.e., a static random access memory (SRAM) device.
2. Description of the Related Art
Conventionally, there is known an SRAM device provided with a memory cell, for example, as shown in FIG. 1.
In FIG. 1, reference 1 denotes a flip-flop circuit; reference 2 a power supply line for supplying a power supply voltage VCC; references 3 and 4 each a resistor functioning as a load element; references 5 and 6 each an nMOS transistor functioning as a driver element; references 7 and 8 each an nMOS transistor functioning as a transfer gate; reference WL a word line; and references BL and BLX each a complementary bit line.
In the illustrated memory cell, a data retention stability in its accessed state (i.e., in its selected state) is determined by the ratio of a current-driving capacity of each driver transistor 5, 6 to a current-driving capacity of each transfer transistor 7, 8. Namely, when the above ratio is greater than 1, it is possible to realize a stable data retention operation (latch operation).
Assuming that a voltage applied to back gates of each driver transistor 5, 6 (hereinafter referred to as a back-bias voltage) is 0 V, a drain current (ID) of each driver transistor 5, 6 is expressed as follows: EQU ID=1/2.times..beta.(VG-VTH).sup.2
Note, VG indicates a gate voltage of each driver transistor, and VTH indicates a threshold voltage thereof.
Accordingly, to increase the current-driving capacity of each driver transistor 5, 6 to thereby realize a stable data retention operation, the threshold voltage VTH of each driver transistor needs to be lowered. For example, so long as the threshold voltage VTH of each driver transistor 5, 6 is not lowered to below 0.9 V when the power supply voltage VCC is 2.5 V, the drain current ID of each driver transistor 5, 6 does not become fully large, and thus it is impossible to realize a stable data retention operation. Also, where the power supply voltage VCC is 2.0 V, the threshold voltage VTH of each driver transistor 5, 6 needs to be lowered to below 0.4 V. Otherwise, the drain current ID of each driver transistor 5, 6 would not become fully large, and thus it would be impossible to realize a stable data retention operation.
Thus, in the memory cell shown in FIG. 1, so long as the threshold voltage VTH of each driver transistor 5, 6 is not lowered, it is impossible to carry out a stable data retention operation under the condition of a lower power supply voltage.
However, where the threshold voltage VTH of each driver transistor 5, 6 is excessively lowered, a problem occurs in that a leak current due to a sub-threshold current remarkably flows in each of non-selected memory cells. Assuming that the gate voltage VG is constant, the sub-threshold current is decreased at the rate of approximately one tenth for an increase of 0.1 V of the threshold voltage VTH. For example, where the gate voltage VG is 0 V, the sub-threshold current in the case of the threshold voltage VTH being 0.4 V becomes large 10.sup.5 times that in the case of the threshold voltage VTH being 0.9 V.
Accordingly, in the VG-ID characteristics in the case of the source voltage being 0 V, it is possible to define the gate voltage VG in the case of the drain current ID being 12 nA, as the threshold voltage VTH.
In this case, when the threshold voltage VTH is 0.4 V and the gate voltage VG is 0 V, the sub-threshold current amounts to 1.2 pA. For example, where the memory device has the capacity of 1M bits, the sum of sub-threshold currents amounts to 1.2 .mu.A. Accordingly, when each memory cell is in its stand-by state, a problem occurs in that a power dissipated in the memory device becomes relatively large.
Also, where the power supply voltage VCC is lowered to 1.5 V, the threshold voltage VTH of each driver transistor 5, 6 needs to be accordingly lowered to 0.1 V to 0 V. Otherwise, it would be impossible to realize a stable data retention operation in a selected state of each memory cell.
However, when the power supply voltage VCC is lowered to 1.5 V, a leak current in each of non-selected memory cells amounts to approximately 20 nA, and thus exceeds 1 nA which is the maximum current value that each load resistor 3, 4 can supply. As a result, a problem occurs in that it is impossible to carry out a data retention operation in a stand-by state (i.e., in a non-selected state) of each memory cell.
Although the above related art is explained by way of an SRAM device as an example, it is not restrictive. Namely, the above explanation and the relevant problem generally apply to a data retention circuit such as a flip-flop circuit, a latch circuit, or the like.